Flash memory is an electronic (solid-state) non-volatile computer storage medium that can be electrically erased and reprogrammed. The NAND flash memory is a main type of flash memory named after the NAND logic gates, it has advantages of fast programming and short erasing time.
FIG. 1 is a schematic diagram showing the composition of a multi-chip package flash array. As a skilled person in the art should understand, several bitlines form a page 10, a plurality of pages form a block 20. A flash memory includes a plurality of blocks. A plane 30 is a storage array which includes a plurality of blocks 20. A chip 40 is formed of several planes 30, and several chips form a package.
As shown in FIG. 2, the NAND flash memory further includes a cache register 60 and a page register 70 for data communication with an external host 50. To obtain a higher degree of performance read operations, the NAND flash memory's cache register 60 and data register 70 can be used independent of each other. Data can be read out from the cache register 60, while array data is transferred from the pages 10 to the data register 70.
The ONFI standard supports a cache read mode of the NAND flash memory. The cache read mode starts with issuing a page read command (00h-30h) to transfer a page of data from NAND flash array to the page register. RY#BY signal will go low during data transfer indicating a busy status. Copying the next page of data from the NAND flash array to the data register while making the cache register page data available is done by issuing either a sequential cache read (31h) or random cache read (00h-31h) command. The sequential cache read mode will copy the next page of data in sequence from the NAND flash array to the data register or use the random cache read mode (00h-31h) to copy a random page of data from the NAND flash array to the data register. The RY#BY signal goes low for a period of tRCBSY during the page data transfer from the NAND flash array to the data register. When RY#BY goes high, this means the cache register is available and can be read out of the cache register by toggling #RE, which starts at address column 0.
At this point in the procedure when completing the read of the desired number of bytes, one or two things can be chosen. Continue cache read (31h or 00h-31h) operations or end the cache read mode with a last address cache read (3Fh) command.
To continue with the read operations, execute the cache read mode (31h or 00h-31h) command. The RY#BY signal goes low for a period of tRCBSY during the page data transfer from the NAND flash array to the data register and the next page of data starts being copied from the NAND flash array to the data register. When RY#BY goes high, this means the cache register is available and can be read out of the cache register by toggling #RE, which starts at address column 0.
To terminate the cache read operations at the last address cache read (3Fh) command is issued. The RY#BY signal goes low and the data register content is copied to the cache register. At the completion of the data register to cache register transfer, RY#BY goes high indicating data is available at the output of the cache register. At this point the data can be read by toggling RE# starting at column address 0 or using the random data output command for random column address access. The NAND flash array is ready for next command set.
The sequential cache read (31h) copies the next page of data in sequence with blocks to the data register while the previous page of data in the cache register is available for output. This is done by issuing the command (31h), RY#BY signal goes low and the status register bits 6 and 5=“00” for the period of tRCBSY. When the RY#BY signal goes high and the status register bits 6 and 5=“10”, data at the cache register is available. The data can be read of from the cache register by toggling #RE, starting address is column 0 or by using the random data output command for random column address access.
The last address cache read (3Fh) copies a page of data from the data register to cache register without starting another cache read. After writing the 3Fh command, RY#BY signal goes low and the status register bits 6 and 5=“00” for the period of tRCBSY. When the RY#BY signal goes high and the status register bits 6 and 5=“11” the cache register data is available and the device NAND flash array is in ready state. The data can read out from the cache register by toggling #RE, starting address is column 0.
With reference to FIG. 3, which is a schematic diagram showing the operation of cache read command in the conventional technology. Based on the above principles, it is obvious that the ONFI cache read command in the conventional technology may automatically read the next page until reaching the last page of the block (shown as the top page in FIG. 3). That is, the cache read operation stops at the last page of block.
However, in some situation, when it is required to read blocks, planes, chips of the package for many times, such as 1000,000 times, stopping in the last page of each block may cause read disturb, which affects correction of the data stored in the last page.